| Tutorial Project: Designing Sample-And-Hold Circuits
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Objective: In this project, you will build several sample-and-hold circuits using switching devices.
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Concepts/Features:
- Analog Switch
- Sampling
- Sample-and-Hold Circuit
- FET Switch
- Operational Amplifier
- Voltage Follower
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Minimum Version Required: All versions
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' Download Link: Mixed-Signal Lesson 4
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What You Will Learn
In this tutorial you will use SPICE's standard voltage-controlled switch as well as a semiconductor FET switch to sample signals and build sample-and-hold (S/H) circuits.
Using the Voltage-Controlled Switch to Sampling Signals
The following is a list of parts needed for this part of the tutorial lesson:
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| Part Name
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Part Type
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Part Value
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| VS
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Voltage Source
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Waveform TBD
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| VC
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Voltage Source
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Waveform TBD
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| RS
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Resistor
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1k
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| RL
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Resistor
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5k
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| S1
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Voltage-Controlled Switch
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Defaults
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| VIN
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Voltage Probe Marker
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N/A
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| VOUT
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Voltage Probe Marker
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N/A
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| VCTRL
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Voltage Probe Marker
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N/A
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The voltage-controlled switch with the keyboard shortcut S is a two-pin device, whose ON and OFF states are controlled by an external voltage defined in the switch's property dialog. VS is the signal source with a sinusoidal waveform. VC is the control source with a pulse waveform, which will control the opening and closing of the switch S1. Open the property dialog of the switch and set its On Voltage and Off Voltage to 4.5V and 0.1V, respectively. These are the threshold values for the control voltage. Set the On Resistance and Off Resistance values of the switch to 1u and 1G, respectively. Finally, set the Controlling Voltage by choosing "VC" from the drop-down box labeled "Voltage across part".
 The property dialog of the voltage-controlled switch. |
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Always set a nonzero value for the On Resistance of the switch. Otherwise, a zero resistance may lead to simulation failure.
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Place and connect all the parts as shown in the figure below:
 A simple sampling circuit using a voltage-controlled switch. |
Set the waveforms of the two voltage source VS and VC as specified below:
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VS
| Offset Voltage
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0
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| Peak Amplitude
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5
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| Frequency
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1k
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| Delay Time
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0
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| Damping Factor
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0
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VC
| Initial Voltage
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0
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| Peak Voltage
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1
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| Delay Time
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0
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| Rise Time
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1p
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| Fall Time
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1p
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| Pulse Width
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1m
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| Pulse Period
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3m
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Run a Transient Test of this circuit with the parameters specified below:
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| Start Time
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0
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| Stop Time
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5m
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| Linearize Step
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1u
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| Step Ceiling
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1u
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| Preset Graph Plots
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v(VIN), v(VOUT), v(VCTRL)
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The results are shown in the figure below. As you can see from the figure, every 3ms the switch closes for a duration of 1ms, and the source voltage is transferred to the resistive load through the voltage divider. Your sinusoidal input signal is clearly under-sampled.
 The input, control and output voltages of the sampling circuit with a sampling period of 3ms. |
Next, change the period and pulse width of the control source according to the table below. Run another transient test with the same parameters. You can see from the figure below that each period of your is sinusoidal input signal is sampled 10 times.
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VC
| Initial Voltage
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0
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| Peak Voltage
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1
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| Delay Time
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0
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| Rise Time
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1p
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| Fall Time
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1p
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| Pulse Width
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50u
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| Pulse Period
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150u
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 The input, control and output voltages of the sampling circuit with a sampling period of 150μs. |
Building a Basic Sample-And-Hold Circuit
Adding a shunt capacitor C1 to the load of your sampling circuit above will make a basic sample-and-hold circuit as shown in the figure below. During the ON state of the switch (Sample Time), the capacitor C will charge to the sampled voltage value. During the OFF state of the switch (Hold Time), the capacitor will keep its held sample voltage until the next charging period. Set the capacitance initially to C1 = 50nF.
 A basic sample-and-hold circuit using a voltage-controlled switch. |
Change the control pulse waveform according to the table below:
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VC
| Initial Voltage
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0
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| Peak Voltage
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1
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| Delay Time
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0
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| Rise Time
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1p
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| Fall Time
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1p
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| Pulse Width
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25p
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| Pulse Period
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50p
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Run a Transient Test of this circuit with the parameters specified below:
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| Start Time
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0
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| Stop Time
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5m
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| Linearize Step
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1u
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| Step Ceiling
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1u
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| Preset Graph Plots
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v(VIN), v(VOUT), v(VCTRL)
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As you can see from this figure, the capacitor discharges too quickly during the hold time and certainly is not able to hold the sampled voltage for the entire time. Note that the time constant of this circuit is τ = RLC1 = 250μs. Of the 50μs period of the pulse waveform, the first 25μs is the sample time, and the remaining 25μs is the hold time. Clearly, the discharge time constant is too short.
 The input, control and output voltages of the basic S/H circuit with C1 = 50nF. |
Next, increase the value of C1 to 400nF. In this case, the discharge time constant will increase to τ = 2ms. Run a new transient test of the circuit with the same parameters as before, and you will get the results shown in the figure below. You can see an improvement of the performance of your S/H circuit but in exchange for lower amplitude and larger delay time.
 The input, control and output voltages of the basic S/H circuit with C1 = 400nF. |
Building an Op-Amp Sample-And-Hold Circuit
The following is a list of parts needed for this part of the tutorial lesson:
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| Part Name
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Part Type
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Part Value
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| VS
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Voltage Source
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Waveform TBD
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| VC
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Voltage Source
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Waveform TBD
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| C1
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Capacitor
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1n
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| D1
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Generic Diode
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Defaults
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| J1
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Generic N-Type JFET
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Defaults
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| Vcc
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DC Bias Voltage Source
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15V
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| Vee
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DC Bias Voltage Source
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-15V
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| X1 - X2
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AD711 Op-Amp
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Defaults
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| VIN
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Voltage Probe Marker
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N/A
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| VOUT
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Voltage Probe Marker
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N/A
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| VCTRL
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Voltage Probe Marker
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N/A
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Configure the two Op-Amps as voltage followers acting as buffers between the input and output as shown in the figure below. The JFET transistor J1 acts as the switch which turns on and off by the control voltage applied to its gate. The shunt charge capacitor is connected between the output of the switch and the input of the second voltage follower.
 A sample-and-hold circuit with Op-Amps and a FET Switch. |
Set the waveforms of the two voltage sources VS and VC as specified below:
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VS
| Offset Voltage
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0
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| Peak Amplitude
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5
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| Frequency
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1k
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| Delay Time
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0
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| Damping Factor
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0
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VC
| Initial Voltage
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0
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| Peak Voltage
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1
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| Delay Time
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0
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| Rise Time
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1p
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| Fall Time
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1p
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| Pulse Width
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5u
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| Pulse Period
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50u
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Run a Transient Test of this circuit with the parameters specified below:
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| Start Time
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0
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| Stop Time
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5m
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| Linearize Step
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1u
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| Step Ceiling
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1u
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| Preset Graph Plots
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v(VIN), v(VOUT), v(VCTRL)
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The simulation results are shown in the figure below. As you can see from the graph, the Op-Amp S/H circuit performs much better than the basic S/H circuit of the previous part and does not introduce any delay or attenuation to the output signal.
 The input, control and output voltages of the Op-Amp S/H circuit with C1 = 1nF. |
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