Difference between revisions of "Mixed-Signal Tutorial Lesson 5: Exploring a 3-Bit A/D Converter Circuit"

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(→‎Building a Ladder A/D Converter)
(→‎Adding the Logic Decoder)
 
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{{projectinfo|Tutorial| Exploring a 3-Bit A/D Converter Circuit |MixTUT4 5.png|In this project, the basic concepts of RF.Spice A/D are demonstrated, and a simple voltage divider is modeled and examined.|
+
{{projectinfo|Tutorial| Exploring a 3-Bit A/D Converter Circuit |MixTUT5 15.png|In this project, you will build and test an A/D converter using commercial integrated circuits.|
  
−
*Analog Switch
+
*Analog-to-Digital Converter
−
*Sampling
+
*Voltage Comparator
−
*Sample-and-Hold Circuit
+
*Ladder Resistive Network
−
*FET Switch
+
*Logic Decoder
−
*Operational Amplifier 
+
|All versions|{{download|http://www.emagtech.com/downloads/ProjectRepo/MixedLesson5.zip Mixed-Signal Lesson 5}} }}
−
*Voltage Follower
+
−
|All versions|{{download|http://www.emagtech.com/content/project-file-download-repository|Mixed-Signal Tutorial Lesson 5|[[RF.Spice A/D]] R15}} }}
+
  
 
=== What You Will Learn ===
 
=== What You Will Learn ===
Line 73: Line 71:
 
</table>
 
</table>
  
−
With V2 = 1V and V1 = 2V, run a live simulation of this circuit and enable '''Show Voltage Text'''. From the figures below, you can see that the output voltage is about 0.1V or at "low state", because V2 < V1. Next, change the source voltage of V2 to 2.1V. This time, you will see the output voltage jump to +5V, which is the voltage of Vcc.   
+
With V2 = 1V and V1 = 2V, run a live simulation of this circuit and enable '''Show Voltage Text'''. From the figures below, you can see that the output voltage is less than 0.1V or at "low state", because V2 < V1. Next, change the source voltage of V2 to 2.1V. This time, you will see the output voltage jump to +5V, which is the voltage of Vcc.   
  
 
<table>
 
<table>
Line 139: Line 137:
 
The voltage source VPOS and VNEG are set to the highest and lowest values of your analog signal, which are +1V and -1V, respectively. The resistive ladder network made up of R1 to R8 provides incremental voltages from -1V to +1V with successive steps of 0.25V. Therefore, you have 8 = 2<sup>3</sup> distinct voltage levels corresponding to 3 binary bits. VS is your analog signal source, whose voltage is compared to all these 8 distinct voltage levels. The outputs of the comparators are then converted to binary values using the 7 A/D bridges.  
 
The voltage source VPOS and VNEG are set to the highest and lowest values of your analog signal, which are +1V and -1V, respectively. The resistive ladder network made up of R1 to R8 provides incremental voltages from -1V to +1V with successive steps of 0.25V. Therefore, you have 8 = 2<sup>3</sup> distinct voltage levels corresponding to 3 binary bits. VS is your analog signal source, whose voltage is compared to all these 8 distinct voltage levels. The outputs of the comparators are then converted to binary values using the 7 A/D bridges.  
  
−
Place and connect all the part as shown in the figure below:  
+
Place and connect all the part as shown in the figure below. When placing the LM393 parts, don't use the half-package devices and place all new devices.  
  
 
<table>
 
<table>
Line 148: Line 146:
 
</tr>
 
</tr>
 
</table>
 
</table>
 +
 +
Set the voltage of the signal source VS to +0.45V and then -0.45V. Run live simulations of each case and observe the state of digital outputs: 
  
 
<table>
 
<table>
Line 162: Line 162:
 
</table>
 
</table>
  
 +
== Adding the Logic Decoder ==
  
 +
The following is a list of parts needed for this part of the tutorial lesson:
  
−
 
−
Set the waveforms of the two voltage source VS and VC as specified below:
 
−
 
−
<table>
 
−
<tr>
 
−
<td>
 
 
{| border="0"
 
{| border="0"
 
|-
 
|-
Line 175: Line 171:
 
|-
 
|-
 
{| class="wikitable"
 
{| class="wikitable"
−
|+ VS
 
 
|-
 
|-
−
! scope="row"| Offset Voltage
+
! scope="col"| Part Name
−
| 0
+
! scope="col"| Part Type
 +
! scope="col"| Part Value
 
|-
 
|-
−
! scope="row"| Peak Amplitude
+
! scope="row"| VS
−
| 5
+
| Voltage Source
 +
| Value TBD
 
|-
 
|-
−
! scope="row"| Frequency
+
! scope="row"| VPOS
−
| 1k
+
| Voltage Source
 +
| +1
 
|-
 
|-
−
! scope="row"| Delay Time
+
! scope="row"| VNEG
−
| 0
+
| Voltage Source
 +
| -1
 
|-
 
|-
−
! scope="row"| Damping Factor
+
! scope="row"| VCC
−
| 0
+
| DC Bias Voltage Source
−
|}
+
| 5
−
</td>
+
−
<td>
+
−
<p> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; </p>
+
−
</td>
+
−
<td>
+
−
{| border="0"
+
 
|-
 
|-
−
| valign="top"|
+
! scope="row"| R1 - R8
 +
| Resistor
 +
| 100
 
|-
 
|-
−
{| class="wikitable"
+
! scope="row"| R9 - R15
−
|+ VC
+
| Resistor
 +
| 2K
 
|-
 
|-
−
! scope="row"| Initial Voltage
+
! scope="row"| X1 - X7
−
| 0
+
| LM393 Differential Voltage Comparator
 +
| Defaults
 
|-
 
|-
−
! scope="row"| Peak Voltage
+
! scope="row"| A1 - A6
−
| 1
+
| Generic XOR Gate
 +
| Defaults
 
|-
 
|-
−
! scope="row"| Delay Time
+
! scope="row"|A7 - A9 , A11
−
| 0
+
| Generic AND Gate
 +
| Defaults
 
|-
 
|-
−
! scope="row"| Rise Time
+
! scope="row"| A10
−
| 1p
+
| Generic XNOR Gate
 +
| Defaults
 
|-
 
|-
−
! scope="row"| Fall Time
+
! scope="row"| A12 - A14
−
| 1p
+
| Generic OR Gate
−
|-
+
| Defaults
−
! scope="row"| Pulse Width
+
−
| 1m
+
 
|-
 
|-
−
! scope="row"| Pulse Period
+
! scope="row"| B0 - B2
−
| 3m
+
| Digital Output
 +
| N/A
 
|}
 
|}
−
</td>
 
−
</tr>
 
−
</table>
 
  
−
Run a Transient Test of this circuit with the [[parameters]] specified below:  
+
The outputs of the seven comparators are either +5V or less than 0.1V in all cases. In this section, you will add a logic decoder to convert the 7 digital outputs to a 3-bit digital word. The following table shows all the 8 distinct voltage levels, their corresponding signal voltage ranges and their associated 3-bit digital words:
  
 
{| border="0"
 
{| border="0"
Line 237: Line 233:
 
{| class="wikitable"
 
{| class="wikitable"
 
|-
 
|-
−
! scope="row"| Start Time
+
! scope="col"| Signal Voltage Range
 +
! scope="col"| Voltage Level Index
 +
! scope="col"| B2
 +
! scope="col"| B1
 +
! scope="col"| B0
 +
|-
 +
| -1V < VS < -0.75V
 +
| 0
 +
| 0
 +
| 0
 
| 0
 
| 0
 
|-
 
|-
−
! scope="row"| Stop Time
+
| -0.75V < VS < -0.50V
−
| 5m
+
| 1
 +
| 0
 +
| 0
 +
| 1
 
|-
 
|-
−
! scope="row"| Linearize Step
+
| -0.50V < VS < -0.25V
−
| 1u
+
| 2
−
|-
+
−
! scope="row"| Step Ceiling
+
−
| 1u
+
−
|-
+
−
! scope="row"| Preset Graph Plots
+
−
| v(VIN), v(VOUT), v(VCTRL)
+
−
|}
+
−
 
+
−
The results are shown in the figure below. As you can see from the figure, every 3ms the switch closes for a duration of 1ms, and the source voltage is transferred to the resistive load through the voltage divider. Your sinusoidal input signal is clearly under-sampled.
+
−
 
+
−
<table>
+
−
<tr>
+
−
<td>
+
−
[[File:MixTUT4 4.png|thumb|750px|The input, control and output voltages of the sampling circuit with a sampling period of 3ms.]]
+
−
</td>
+
−
</tr>
+
−
</table>
+
−
 
+
−
Next, change the period and pulse width of the control source according to the table below. Run another transient test with the same [[parameters]]. You can see from the figure below that each period of your is sinusoidal input signal is sampled 10 times.       
+
−
 
+
−
{| border="0"
+
−
|-
+
−
| valign="top"|
+
−
|-
+
−
{| class="wikitable"
+
−
|+ VC
+
−
|-
+
−
! scope="row"| Initial Voltage
+
 
| 0
 
| 0
−
|-
 
−
! scope="row"| Peak Voltage
 
 
| 1
 
| 1
 +
| 0
 
|-
 
|-
−
! scope="row"| Delay Time
+
| -0.25V < VS < 0V
 +
| 3
 
| 0
 
| 0
 +
| 1
 +
| 1
 
|-
 
|-
−
! scope="row"| Rise Time
+
| 0V < VS < 0.25V
−
| 1p
+
| 4
−
|-
+
| 1
−
! scope="row"| Fall Time
+
| 0
−
| 1p
+
−
|-
+
−
! scope="row"| Pulse Width
+
−
| 50u
+
−
|-
+
−
! scope="row"| Pulse Period
+
−
| 150u
+
−
|}
+
−
 
+
−
<table>
+
−
<tr>
+
−
<td>
+
−
[[File:MixTUT4 5.png|thumb|750px|The input, control and output voltages of the sampling circuit with a sampling period of 150&mu;s.]]
+
−
</td>
+
−
</tr>
+
−
</table>
+
−
 
+
−
== Building a Basic Sample-And-Hold Circuit ==
+
−
 
+
−
Adding a shunt capacitor C1 to the load of your sampling circuit above will make a basic sample-and-hold circuit as shown in the figure below. During the ON state of the switch (Sample Time), the capacitor C will charge to the sampled voltage value. During the OFF state of the switch (Hold Time), the capacitor will keep its held sample voltage until the next charging period. Set the capacitance initially to C1 = 50nF.
+
−
 
+
−
<table>
+
−
<tr>
+
−
<td>
+
−
[[File:MixTUT4 6.png|thumb|560px| A basic sample-and-hold circuit using a voltage-controlled switch.]]
+
−
</td>
+
−
</tr>
+
−
</table>
+
−
 
+
−
Change the control pulse waveform according to the table below:
+
−
 
+
−
{| border="0"
+
−
|-
+
−
| valign="top"|
+
−
|-
+
−
{| class="wikitable"
+
−
|+ VC
+
−
|-
+
−
! scope="row"| Initial Voltage
+
 
| 0
 
| 0
 
|-
 
|-
−
! scope="row"| Peak Voltage
+
| 0.25V < VS < 0.50V
 +
| 5
 
| 1
 
| 1
−
|-
 
−
! scope="row"| Delay Time
 
 
| 0
 
| 0
 +
| 1
 
|-
 
|-
−
! scope="row"| Rise Time
+
| 0.50V < VS < 0.75V
−
| 1p
+
| 6
−
|-
+
| 1
−
! scope="row"| Fall Time
+
| 1
−
| 1p
+
−
|-
+
−
! scope="row"| Pulse Width
+
−
| 25p
+
−
|-
+
−
! scope="row"| Pulse Period
+
−
| 50p
+
−
|}
+
−
 
+
−
Run a Transient Test of this circuit with the [[parameters]] specified below:
+
−
 
+
−
{| border="0"
+
−
|-
+
−
| valign="top"|
+
−
|-
+
−
{| class="wikitable"
+
−
|-
+
−
! scope="row"| Start Time
+
 
| 0
 
| 0
 
|-
 
|-
−
! scope="row"| Stop Time
+
| 0.75V < VS < 1V
−
| 5m
+
| 7
−
|-
+
| 1
−
! scope="row"| Linearize Step
+
| 1
−
| 1u
+
| 1
−
|-
+
−
! scope="row"| Step Ceiling
+
−
| 1u
+
−
|-
+
−
! scope="row"| Preset Graph Plots
+
−
| v(VIN), v(VOUT), v(VCTRL)
+
 
|}
 
|}
  
−
As you can see from this figure, the capacitor discharges too quickly during the hold time and certainly is not able to hold the sampled voltage for the entire time. Note that the time constant of this circuit is &tau; = R<sub>L</sub>C1 = 250&mu;s. Of the 50&mu;s period of the pulse waveform, the first 25&mu;s is the sample time, and the remaining 25&mu;s is the hold time. Clearly, the discharge time constant is too short.
+
If we denote the outputs of the seven comparators X1 - X7 by c1 - c7, it is not difficult to verify the following relationships:
  
−
<table>
+
<math> b0 = \left( \left( (c1\oplus c2) \oplus (c3\oplus c4) \right) \oplus (c5\oplus c6) \right) \oplus c7 </math>
−
<tr>
+
−
<td>
+
−
[[File:MixTUT4 7.png|thumb|750px|The input, control and output voltages of the basic S/H circuit with C1 = 50nF.]]
+
−
</td>
+
−
</tr>
+
−
</table>
+
  
−
Next, increase the value of C1 to 400nF. In this case, the discharge time constant will increase to &tau; = 2ms. Run a new transient test of the circuit with the same [[parameters]] as before, and you will get the results shown in the figure below. You can see an improvement of the performance of your S/H circuit but in exchange for lower amplitude and larger delay time.          
+
<math> b1 = (c1. c2) \ . \left( \ (c3. c4) \bar{\oplus} (c5. c6) \  \right) </math> 
  
−
<table>
+
<math> b2 = (c4 + c5) + (c6 + c7) </math>
−
<tr>
+
−
<td>
+
−
[[File:MixTUT4 8.png|thumb|750px|The input, control and output voltages of the basic S/H circuit with C1 = 400nF.]]
+
−
</td>
+
−
</tr>
+
−
</table>
+
  
−
== Building an Op-Amp Sample-And-Hold Circuit ==
+
where b0, b1 and b2 are the three bit of the output digital word.
−
 
+
−
The following is a list of parts needed for this part of the tutorial lesson:
+
−
 
+
−
{| border="0"
+
−
|-
+
−
| valign="top"|
+
−
|-
+
−
{| class="wikitable"
+
−
|-
+
−
! scope="col"| Part Name
+
−
! scope="col"| Part Type
+
−
! scope="col"| Part Value
+
−
|-
+
−
! scope="row"| VS
+
−
| Voltage Source
+
−
| Waveform TBD
+
−
|-
+
−
! scope="row"| VC
+
−
| Voltage Source
+
−
| Waveform TBD
+
−
|-
+
−
! scope="row"| C1
+
−
| Capacitor
+
−
| 1n
+
−
|-
+
−
! scope="row"| D1
+
−
| Generic Diode
+
−
| Defaults
+
−
|-
+
−
! scope="row"| J1
+
−
| Generic N-Type JFET
+
−
| Defaults
+
−
|-
+
−
! scope="row"| Vcc
+
−
| DC Bias Voltage Source
+
−
| 15V
+
−
|-
+
−
! scope="row"| Vee
+
−
| DC Bias Voltage Source
+
−
| -15V
+
−
|-
+
−
! scope="row"| X1 - X2
+
−
| AD711 Op-Amp
+
−
| Defaults
+
−
|-
+
−
! scope="row"| VIN
+
−
| Voltage Probe Marker
+
−
| N/A
+
−
|-
+
−
! scope="row"| VOUT
+
−
| Voltage Probe Marker
+
−
| N/A
+
−
|-
+
−
! scope="row"| VCTRL
+
−
| Voltage Probe Marker
+
−
| N/A
+
−
|}
+
  
−
Configure the two Op-Amps as voltage followers acting as buffers between the input and output as shown in the figure below. The JFET transistor J1 acts as the switch which turns on and off by the control voltage applied to its gate. The shunt charge capacitor is connected between the output of the switch and the input of the second voltage follower.  
+
Place and connect all the parts as shown in the figure below. Note that you don't need the ADC bridges for this part because [[RF.Spice A/D]] automatically takes care of A/D conversions due to the presence of the logic gates in combination with the analog parts. You can use the circuit from the previous part, remove the ADC bridges and add all the new gates listed above.  
  
 
<table>
 
<table>
 
<tr>
 
<tr>
 
<td>
 
<td>
−
[[File:MixTUT4 11.png|thumb|550px| A sample-and-hold circuit with Op-Amps and a FET Switch.]]
+
[[File:MixTUT5 15.png|thumb|750px|The ladder A/D circuit with logic decoder.]]
 
</td>
 
</td>
 
</tr>
 
</tr>
 
</table>
 
</table>
  
−
Set the waveforms of the two voltage sources VS and VC as specified below:
+
Set various values for the signal voltage and run live simulations of your circuit. In the figure below, the voltage animation is shown for the cases VS = -0.17V and VS = +0.82V. Their corresponding digital words are 011 and 111, respectively.
  
 
<table>
 
<table>
 
<tr>
 
<tr>
 
<td>
 
<td>
−
{| border="0"
+
[[File:MixTUT5 16.png|thumb|750px|The binary output of the ladder A/D circuit with logic decoder with VS = -0.17V.]]
−
|-
+
−
| valign="top"|
+
−
|-
+
−
{| class="wikitable"
+
−
|+ VS
+
−
|-
+
−
! scope="row"| Offset Voltage
+
−
| 0
+
−
|-
+
−
! scope="row"| Peak Amplitude
+
−
| 5
+
−
|-
+
−
! scope="row"| Frequency
+
−
| 1k
+
−
|-
+
−
! scope="row"| Delay Time
+
−
| 0
+
−
|-
+
−
! scope="row"| Damping Factor
+
−
| 0
+
−
|}
+
−
</td>
+
−
<td>
+
−
<p> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; </p>
+
−
</td>
+
−
<td>
+
−
{| border="0"
+
−
|-
+
−
| valign="top"|
+
−
|-
+
−
{| class="wikitable"
+
−
|+ VC
+
−
|-
+
−
! scope="row"| Initial Voltage
+
−
| 0
+
−
|-
+
−
! scope="row"| Peak Voltage
+
−
| 1
+
−
|-
+
−
! scope="row"| Delay Time
+
−
| 0
+
−
|-
+
−
! scope="row"| Rise Time
+
−
| 1p
+
−
|-
+
−
! scope="row"| Fall Time
+
−
| 1p
+
−
|-
+
−
! scope="row"| Pulse Width
+
−
| 5u
+
−
|-
+
−
! scope="row"| Pulse Period
+
−
| 50u
+
−
|}
+
 
</td>
 
</td>
 
</tr>
 
</tr>
−
</table>
 
−
 
−
Run a Transient Test of this circuit with the [[parameters]] specified below:
 
−
 
−
{| border="0"
 
−
|-
 
−
| valign="top"|
 
−
|-
 
−
{| class="wikitable"
 
−
|-
 
−
! scope="row"| Start Time
 
−
| 0
 
−
|-
 
−
! scope="row"| Stop Time
 
−
| 5m
 
−
|-
 
−
! scope="row"| Linearize Step
 
−
| 1u
 
−
|-
 
−
! scope="row"| Step Ceiling
 
−
| 1u
 
−
|-
 
−
! scope="row"| Preset Graph Plots
 
−
| v(VIN), v(VOUT), v(VCTRL)
 
−
|}
 
−
 
−
The simulation results are shown in the figure below. As you can see from the graph, the Op-Amp S/H circuit performs much better than the basic S/H circuit of the previous part and does not introduce any delay or attenuation to the output signal. 
 
−
 
 
−
<table>
 
 
<tr>
 
<tr>
 
<td>
 
<td>
−
[[File:MixTUT4 12.png|thumb|800px|The input, control and output voltages of the Op-Amp S/H circuit with C1 = 1nF.]]
+
[[File:MixTUT5 17.png|thumb|750px|The binary output of the ladder A/D circuit with logic decoder with VS = +0.82V.]]
 
</td>
 
</td>
 
</tr>
 
</tr>
 
</table>
 
</table>
−
 
 
<p>&nbsp;</p>
 
<p>&nbsp;</p>
−
[[Image:Back_icon.png|40px]] '''[[RF.Spice_A/D#RF.Spice_A.2FD_Tutorial | Back to RF.Spice A/D Tutorial Gateway]]'''
+
[[Image:Back_icon.png|40px]] '''[[RF.Spice_A/D#RF.Spice_A.2FD_Tutorials | Back to RF.Spice A/D Tutorial Gateway]]'''

Latest revision as of 14:09, 4 November 2015

Tutorial Project: Exploring a 3-Bit A/D Converter Circuit
MixTUT5 15.png

Objective: In this project, you will build and test an A/D converter using commercial integrated circuits.

Concepts/Features:

  • Analog-to-Digital Converter
  • Voltage Comparator
  • Ladder Resistive Network
  • Logic Decoder

Minimum Version Required: All versions

'Download2x.png Download Link: Mixed-Signal Lesson 5

What You Will Learn

In this tutorial you will use SPICE's standard voltage-controlled switch to sample signals and will build and test sample-and-hold (S/H) circuits.

Testing a Voltage Comparator Integrated Circuit

The following is a list of parts needed for this part of the tutorial lesson:

Part Name Part Type Part Value
V1 Voltage Source 2
V2 Voltage Source 1
VCC DC Bias Voltage Source 5
R1 Resistor 2k
X1 LM393 Differential Voltage Comparator Defaults
VOUT Voltage Probe Marker N/A
The Device & Section dialog.

In Analog Tutorial Lesson 12, you analyzed the operation of an analog voltage comparator integrated circuit. In this project, you will use a commercial voltage comparator IC called LM393 manufactured by Texas Instruments. The DC bias voltage source Vcc determines the comparator's high output voltage. We choose +5V high state voltage for this project. You can access the IC either from Part Bin or using the menu item menu > Parts > Active Devices > Integrated Circuits > LM393 Differential Voltage Comparator. Each LM393 IC package contains two devices. When you place the part, a dialog opens up and asks you whether you want "Section A" or "Section B". If one has been used up earlier, only the other available section will show up in the list. The dialog also gives you options or buttons for New Device and Next Device.

The property dialog of the voltage comparator IC LM393.

Place and connect all the parts as shown in the figure below:

A simple circuit for testing the voltage comparator IC LM393.

With V2 = 1V and V1 = 2V, run a live simulation of this circuit and enable Show Voltage Text. From the figures below, you can see that the output voltage is less than 0.1V or at "low state", because V2 < V1. Next, change the source voltage of V2 to 2.1V. This time, you will see the output voltage jump to +5V, which is the voltage of Vcc.

The output voltage of LM393 when V2 < V1.
The output voltage of LM393 when V2 > V1.

Building a Ladder A/D Converter

The following is a list of parts needed for this part of the tutorial lesson:

Part Name Part Type Part Value
VS Voltage Source Value TBD
VPOS Voltage Source +1
VNEG Voltage Source -1
VCC DC Bias Voltage Source 5
R1 - R8 Resistor 100
R9 - R15 Resistor 2K
X1 - X7 LM393 Differential Voltage Comparator Defaults
A1 - A7 1-Bit A/D Conversion Bridge Defaults, in_high = 4.5
Out1 - Out7 Digital Output N/A

The voltage source VPOS and VNEG are set to the highest and lowest values of your analog signal, which are +1V and -1V, respectively. The resistive ladder network made up of R1 to R8 provides incremental voltages from -1V to +1V with successive steps of 0.25V. Therefore, you have 8 = 23 distinct voltage levels corresponding to 3 binary bits. VS is your analog signal source, whose voltage is compared to all these 8 distinct voltage levels. The outputs of the comparators are then converted to binary values using the 7 A/D bridges.

Place and connect all the part as shown in the figure below. When placing the LM393 parts, don't use the half-package devices and place all new devices.

The ladder A/D circuit with seven voltage comparators.

Set the voltage of the signal source VS to +0.45V and then -0.45V. Run live simulations of each case and observe the state of digital outputs:

The digital outputs of the ladder A/D circuit with VS = +0.45V.
The digital outputs of the ladder A/D circuit with VS = -0.45V.

Adding the Logic Decoder

The following is a list of parts needed for this part of the tutorial lesson:

Part Name Part Type Part Value
VS Voltage Source Value TBD
VPOS Voltage Source +1
VNEG Voltage Source -1
VCC DC Bias Voltage Source 5
R1 - R8 Resistor 100
R9 - R15 Resistor 2K
X1 - X7 LM393 Differential Voltage Comparator Defaults
A1 - A6 Generic XOR Gate Defaults
A7 - A9 , A11 Generic AND Gate Defaults
A10 Generic XNOR Gate Defaults
A12 - A14 Generic OR Gate Defaults
B0 - B2 Digital Output N/A

The outputs of the seven comparators are either +5V or less than 0.1V in all cases. In this section, you will add a logic decoder to convert the 7 digital outputs to a 3-bit digital word. The following table shows all the 8 distinct voltage levels, their corresponding signal voltage ranges and their associated 3-bit digital words:

Signal Voltage Range Voltage Level Index B2 B1 B0
-1V < VS < -0.75V 0 0 0 0
-0.75V < VS < -0.50V 1 0 0 1
-0.50V < VS < -0.25V 2 0 1 0
-0.25V < VS < 0V 3 0 1 1
0V < VS < 0.25V 4 1 0 0
0.25V < VS < 0.50V 5 1 0 1
0.50V < VS < 0.75V 6 1 1 0
0.75V < VS < 1V 7 1 1 1

If we denote the outputs of the seven comparators X1 - X7 by c1 - c7, it is not difficult to verify the following relationships:

[math] b0 = \left( \left( (c1\oplus c2) \oplus (c3\oplus c4) \right) \oplus (c5\oplus c6) \right) \oplus c7 [/math]

[math] b1 = (c1. c2) \ . \left( \ (c3. c4) \bar{\oplus} (c5. c6) \ \right) [/math]

[math] b2 = (c4 + c5) + (c6 + c7) [/math]

where b0, b1 and b2 are the three bit of the output digital word.

Place and connect all the parts as shown in the figure below. Note that you don't need the ADC bridges for this part because RF.Spice A/D automatically takes care of A/D conversions due to the presence of the logic gates in combination with the analog parts. You can use the circuit from the previous part, remove the ADC bridges and add all the new gates listed above.

The ladder A/D circuit with logic decoder.

Set various values for the signal voltage and run live simulations of your circuit. In the figure below, the voltage animation is shown for the cases VS = -0.17V and VS = +0.82V. Their corresponding digital words are 011 and 111, respectively.

The binary output of the ladder A/D circuit with logic decoder with VS = -0.17V.
The binary output of the ladder A/D circuit with logic decoder with VS = +0.82V.

 

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