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/* Running a Transient Test of the Binary Counter */
{{projectinfo|Tutorial| Building a Binary Counter Using JK Flip-Flops |TUT11-912.png|In this project, you will learn about JK flip-flops and will use them to build a 4-bit binary counter.|
*JK Flip-Flop
*Toggle Flip-Flop
*Binary Counter
*Digital Timing Diagram
*Transient Test
*Time Step Ceiling
|All versions|{{download|http://www.emagtech.com/contentdownloads/project-file-download-repository|EMProjectRepo/DigitalLesson4.Tempo zip Digital Lesson 1|[[EM.Cube]] 14.84}} }}
=== What You Will Learn ===
In this tutorial you will first examine [[RF.Spice]]'s JK flip-flop device and will then use four JK flip-flops to design a 4-bit binary counter. Besides using live timing diagrams, you will also learn how to run a transient analysis of your digital circuit.
== Testing a JK Flip-Flop ==
[[File:TUT11-17.png|thumb|500px|The property dialog of the JK-Type Flip-Flop device.]]
Set the time step to 20ns. Set both input values to zero initially. Run a live [[Digital Simulation|digital simulation]] and observe the timing diagram of the circuit. Step the simulation sequentially until t = 1200ns. Change the input values according to the table below:
{| class="wikitable"
<td>
[[File:TUT11-10.png|thumb|720px|The timing diagram of the JK Flip-Flop circuit.]]
</td>
</tr>
</table>
 
== Operating a JK Flip-Flop as a Toggle Flip-Flop ==
 
If you tie the two J and K inputs of a JK flip-flop together, it becomes equivalent to a T-Type (Toggle) Flip-Flop. A high input represents the "Toggle State", and a low input represents the "Hold State". In other words, when the input is high, the output toggles at the clock's rising edge. In the circuit of the previous part, delete the second digital input "In2". Then connect the K-pin of the flip-flop to its J-pin using the Wire Tool. The resulting circuit is shown in the figure below:
 
<table>
<tr>
<td>
[[File:DigiTUT4_5.png|thumb|480px|The JK-Type flip-flop device configured as a Toggle flip-flop.]]
</td>
</tr>
</table>
 
Activate the live timing diagram and step your digital circuit using the same scheme as in the previous part. The single input data are given in the table below:
 
{| class="wikitable"
|-
! scope="col"| Time
! scope="col"| In1
|-
| 0ns
| 0
|-
| 60ns
| 1
|-
| 160ns
| 0
|-
| 360ns
| 1
|-
| 640ns
| 0
|-
| 800ns
| 0
|-
|}
 
The resulting timing diagram is shown in the figure below. Note that when the input is one, the state of the output toggles on each rising edge of the clock. This happen at instants t = 100ns, 400ns, 500ns and 600ns. Also note the propagation delay that takes the output to toggle its binary state. The low-to-hight propagation delay of the flip-flop is 16ns, while its high-to-low delay is 25ns.
<table>
<tr>
<td>
[[File:DigiTUT4_6.png|thumb|720px|The timing diagram of the JK Flip-Flop circuit configured as a Toggle flip-flop.]]
</td>
</tr>
! scope="row"| CLK
| Digital Clock
| Period = 100ns500ns, Pulse Width = 50ns250ns
|-
! scope="row"| A1 - A4
|}
If you tie the two J and K inputs of a JK flip-flop together, it becomes equivalent to a T-Type (Toggle) Flip-Flop. A high input represents the "Toggle State", and a low input represents the "Hold State". In other words, when the input is high, the output toggles at the clock's rising edge. T flip-flops can be cascaded to build binary counters. In the last part of this tutorial lesson, you will use four JK flip-flops to build a 4-bit binary counter. Tie the J and K pins of all the four flip-flops together and connect them to the output of the Toggle Switch. Set the switch to the "1" (ON) state by clicking on the right side of its symbol. Set the Period of the clock CLK to 500ns and set its Pulse Width to 250ns. In this case, you can neglect the propagation delays compared to the clock period. Connect the digital clock device to the CLK pin of the first flip-flop, and connect output of the first flip-flop to the CLK pin of the second flip-flop. Cascade the four flip-flops in this way and connect all the outputs and inverters as shown in the above figurebelow. The output of the first flip-flop provides the least significant bit B0, and the output of the fourth flip-flop provides the most significant bit B3.
<table>
<tr>
<td>
[[File:TUT11-11DigiTUT4_7.png|thumb|560px|The 4-bit Binary Counter digital circuit.]]
</td>
</tr>
== Running a Transient Test of the Binary Counter ==
[[File:b2TUT4_15.png|thumb|360px|Property Dialog of Digital Source]]Since digital simulations take place in the time domain, besides a live simulation, you can also run a transient test on them. Recall from previous the first few analog tutorial lessons that unlike live simulations, [[tests]] are preplanned simulationsimulations. In other words, in a test, the inputs are completely known and will not cannot change during the period of time when the simulation engine is doing its job. At the end of a test, you will see the final results. Contrast this to a live [[Digital Simulation|digital simulation]], when the engine waits for you to make your next move. Then it responds to your action. For transient test of digital circuit, [[B2.Spice A/D]] offers another type of digital input called a "'''Digital Source'''". A digital source is indeed the same as a digital input except for the fact that it contains a preloaded "'''Time-Value Array'''". This means that a digital source knows in advance what values it will take at certain times during the simulation.
At this pointNext, go back to your circuit and delete all the three digital inputs. Select each part and press open the keyboard's ''Tests'Delete Key'''. Next, from tab of the '''Parts MenuToolbox''', select choose the '''Digital I/OTransient''' submenu and then select "'''Digital Source'''". Place the source in your circuit at the location where you used to have Input 1 test type and connect it to bring up the same wire. Use the keyboard's ''Transient Test Settings'SPACE Bar''' to duplicate panel. Set the digital source twice and place them at parameters for the locations of the old Input 2 and 3. Your digital circuit should now look like the opposite figure.transient test as follows:
Double-click the first digital source to open its property dialog as shown below. {{Note | In the table titled "'''Edit Time-Value Array'''", enter the binary values Transient Test of the source as a function of time according to the state table shown in the previous section. Enter time in nanoseconds and use the values in "Input 1" column for the first digital source. Similarlycircuits, open the property dialogs of the second input and third digital sources and enter their time-value arrays using output signals are automatically added to the values in the "Input 2" and "Input 3" columns of the above table, respectively.  {{Note|The "Time-Value" array of a digital source can be conveniently loaded from a text filegraph signal list.}}
{| border="0"
|-
| valign="bottomtop"|[[File:b2TUT4_17.png|thumb|left|220px|Edit Graph Dialog]]| valign="bottom"|[[File:b2TUT4_18.png|thumb|left|220px|Edit Axis Dialog]]
|-
{| class="wikitable"
|-
! scope="row"| Start Time
| 0
|-
! scope="row"| Stop Time
| 10u
|-
! scope="row"| Linearize Step
| 20n
|-
! scope="row"| Step Ceiling
| 20n
|-
! scope="row"| Preset Graph Plots
| Defaults
|}
[[File:b2TUT4_19Click the Run button to run the transient test.png|thumb|640px| The output following graph of transient analysis will appear at the bottom of the digital circuitWorkshop.]] Next, bring up This is indeed identical to the '''Transient Test''' from timing diagram you viewed in the '''previous step of the lesson. However, this digital graph is a regular [[TestsRF.Spice A/D]] Toolbox'''graph with full analysis and customization capability. For example, you can zoom in on the rising and set falling edges of the [[parameters]] for pulses and examine the test as follows: Start Time: 0propagation delays.
Stop Time: 420n<table><tr>Linearize Step: 1n<td> Step Ceiling[[File: 1n Click the Run button to run the transient testTUT11-12. png|thumb|720px|The following graph will appear at the bottom of the Workshop. This is indeed identical to the transient response or finalized timing diagram you viewed in the previous step of the lesson4-bit Binary Counter. However, this digital graph is a regular [[B2.Spice A/D]] graph with full analysis and customization capability. For example, you can zoom in on the rising and falling edges of the pulses and examine the propagation delays.</td></tr> For this circuit, you will run a Transient Test with start and stop times set to 0 and 10&mu;s and a "Step Ceiling" (or step time) equal to 20ns.  {{Note | In the Transient Test of digital circuits, the input and output signals are automatically added to the graph signal list.}}</table>
Run the test and view the output graph as shown in the figure below. Since the input to all the flip-flops is high at all times, they are always in the toggle state. That means that the output of each flip-flop toggles its value at the rising edge of the clock of the flip-flop, which is itself the output of the previous stage. The first thing you observe from the figure is that each flip-flop functions as a frequency divider. Thus, the four flip-flops work as "Divide By 2", "Divide By 4", "Divide By 8" and "Divide By 16" frequency dividers, respectively, for the input clock CLK.
You have to wait until t = 500ns for all the toggle states to take effect. You can still see the cumulative propagation delays starting at t = 500ns. You will start measuring the outputs B0, B1, B2 and B3 at t = 750ns and at every clock cycle of 500ns thereafter. As you can see from the figure, at t = 750ns, B0 = B1 = B2 = B3 = 0. The 4-bit binary output is thus [B3][B2][B1][B0] = 0. After each rising edge of the input clock signal, the 4-bit binary output [B3][B2][B1][B0] is incremented by one. After 15 clock cycles, you get [B3][B2][B1][B0] = 1111 (equivalent to the decimal 15). After the sixteenth rising edge of the clock, the binary counter resets to zero again (e.g. at t = 8750ns). The results are given in the table below.
[[File:TUT11-12.png|thumb|800px|The timing diagram of the 4-bit Binary Counter.]]
{| class="wikitable"
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<p>&nbsp;</p>
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