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{{projectinfo|Tutorial| Exploring Flip-Flops and Sequential Logic Circuits |TUT11-97.png|In this project, the basic concepts of RF.Spice A/D are demonstrated, and a simple voltage divider is modeled and examined.|

|All versions|{{download|http://www.emagtech.com/contentdownloads/project-file-download-repository|EMProjectRepo/DigitalLesson3.Tempo zip Digital Lesson 1|[[EM.Cube]] 14.83}} }}

<b>Exploring Flip-Flops and Sequential Logic Circuits</b> === Objective What You Will Learn ===

=== Testing a D Flip-Flop ===

! scope="row"| D1A1

This part of the tutorial lesson is very similar to the last part, except for replacing the SR latch with the D flip-flop. You will build a synchronous circuit with a digital clock and a single input as shown in the opposite figurebelow. The keyboard shortcut for digital clock is {{key|Alt+C}}. Set the "Period" of the clock to 100ns and its "Pulse Width" to 50ns. Connect the digital input device to the "D" pin of the flip-flop and the digital output device to its "Q" pin. The D flip-flop transfers the input data at its input to its Q output on the rising edge of the clock pulse. During the rest of the clock cycle, the output remains unchanged (hold state).

[[File:TUT11-15.png|thumb|500px|The property dialog of the D-Type Flip-Flop device.]] To understand the operation of the flip-flop circuit, you will use the "Live Digital Timing Diagram" feature of [[RF.Spice A/D]]. FirstAs you earned in the previous tutorial lesson, click the button labeled "'''...'''" on the '''[[Toolbars#Main_Toolbar| Main Toolbar]]''' on the left of the Run button or use the keyboard shortcut "Ctrl+I" to open the "Simulation Time Options" dialog. Set set the step time to 20ns. Set the input initially to In1 = 0. Then, to activate the timing diagram, click the "'''Show/Hide Live Digital Timing Diagrams'''" [[File:b2Timing_Tool.png]] button of the '''[[Toolbars#Schematic_Toolbar |Schematic Toolbar]]'''. Remember that nothing will happen until you start a [[Digital Simulation|digital simulation]]. Click the "'''Step'''" [[File:b2Step_Tool.png]] button of the '''[[Toolbars#Main_Toolbar |Main Toolbar]]''' or use the keyboard shortcut "{{key|Ctrl+H" }} to advance the simulation time one step at a time. Step the simulation time to 60ns and then change the input to In1 = 1. Keep stepping to 160ns and then change the input to In1 = 0 again. Continue stepping to 400ns and change the input to In1 = 1 once again and then proceed to 600ns. The table below summarizes the input entries:   [[File:TUT11-6.png|thumb|800px|The digital timing diagram of the single D-Type Flip-Flop circuit.]] [[File:TUT11-15.png|thumb|400px|The property dialog of the D-Type Flip-Flop device.]] {{Note|The timing diagram updates only when there is a change of states of the inputs.}} 

The timing diagram of your D flip-flop circuit is shown in the above figurebelow. As you can see from the figure, the input first rises from 0 to 1 at t = 160ns. The flip-flop waits until the next rising edge of the clock signal at t = 200ns. The input's high state is transferred to the output Q with a propagation delay of 14ns. According to the property dialog of the D Flip-Flop device, the low-to-high propagation delay of the device is tPLH = 14ns, while its high-to-low propagation delay is tPHL = 1420ns. Therefore, Q rises from 0 to 1 at t = 214ns and stays high for the next several clock cycles. The input next falls from 1 to 0 at t = 260ns. The flip-flop waits until the next rising edge of the clock signal at t = 300ns. The input's low state is transferred to the output Q with a propagation delay of 20ns. Therefore, Q falls from 1 to 0 at t = 320ns and stays low for the next several clock cycles. The input rises again from 0 to 1 at t = 400ns and stay high for the rest of the simulation time. This time the flip-flop has to wait a full clock period until the next rising edge of the clock signal at t = 500ns. The input's high state is transferred to the output Q with a propagation delay of 14ns. Then, Q rises again from 0 to 1 at t = 514ns and stays high for the rest of the simulation time.

B2.Spice's digital timing diagrams are live graphs that evolve in real time. When you step the simulation for too long, the diagram exceeds the extents of your screen, and a horizontal scroll bar soon appears at the bottom of the diagram. To see the whole diagram without scrolling, you can zoom out its view horizontally. Click on the tab of the diagram at the bottom window to make its view active. The [[Toolbars#Graph_Toolbar|Graph Toolbar]] appears and replaces the [[Toolbars#Schematic_Toolbar|Schematic Toolbar]]. Click the "Zoom Out Horizontally" <table><tr><td>[[File:TUT11-166.png]] button of the [[Toolbars#Graph_Toolbar|Graph Toolbar]] to squeeze the thumb|720px|The digital timing diagram horizontally to of the point it fits in the screensingle D-Type Flip-Flop circuit.]] </td></tr></table>

=== Building a 4-Bit Shift Register Using D Flip-Flops ===

{| border="0"|-| valign="top"||-{| class="wikitable"|-! scope="col"| Part Name! scope="col"| Part Type! scope="col"| Part Value|-! scope="row"| Data| Digital Input| 1-bit|-! scope="row"| B0 - B3| Digital Output| N/A|-! scope="row"| CLK| Digital Clock| Period = 100ns, Pulse Width = 50ns|-! scope="row"| A1 - A4| D-Type Flip-Flop| Defaults|}

Digital Input: Data A shift register is a multi-output digital circuit that transfer the input data to its outputs sequentially at each clock cycle. Cascade the four D flip-flops as shown on the figure by connecting the Q pin of each to the D pin of the next. All four flip-flops share the same clock signal. Use the same clock settings from the previous part (keyboard shortcut: NPeriod = 100ns and Pulse Width = 50ns). Set the step time to 20ns. Enable the live digital timing diagram. Run a digital simulation and step through 1200ns. Set the value of the input "Data" to 0 and change it to 1 at t = 100ns and change it back to 0 at t = 600ns.

Digital Clock: CLK (keyboard shortcut: Alt+C)<table><tr>Four D-Type Flip-Flops<td> Four Digital Output[[File: B0, B1, B3 and B4 (keyboard shortcut: O) TUT11-7.png|thumb|640px|The 4--- A bit shift register is a multi-output digital circuit that transfer the input data to its outputs sequentially at each clock cycle. Cascade the four D flip-flops as shown on the figure by connecting the Q pin of each to the D pin of the next. All four flip-flops share the same clock signal. Use the same clock settings from the previous part (Period = 100ns and Pulse Width = 50ns). Set the step time to 20ns. Enable the live digital timing diagram. Run a [[Digital Simulation|digital simulation]] and step through 1200ns. Set the value of the input "Data" to 0 and change it to 1 at t = 100ns and change it back to 0 at t = 600ns. </td></tr></table>

[[File:TUT11-8.png|thumb|800px720px|The timing diagram of the 4-bit shift register circuit.]]

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