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[[RF.Spice A/D]] provides an extensive library of black-box virtual blocks that allow you to quickly test and verify new system concepts without getting into the details of particular circuit realizations. A virtual block typically has one or more input pins and one or more output pins. It models a system-level function or behavior in the form of a relationship between the input and output voltages. For example, a multiplier block takes two input voltages and outputs their product. An analog frequency doubler takes a single sinusoidal input voltage and produces a sinusoidal output voltage whose frequency is twice as large as the input frequency. A real practical frequency doubler typically involves a sophisticated circuit either with discrete components or in the form of an integrated circuit. In many situations like system design, you simply need a "black box" that exhibits the behavior of a frequency doubler just to try out and verify a system concept. You would worry about the hardware implementation of your block at a later time after the proof of concept has been established. [[RF.Spice]]'s virtual blocks will prove very useful when you design complex systems that contain many subcircuits and subsystems. One of the great strengths of [[RF.Spice A/D]] is the ease of creating new user-defined devices or models. Most of RF.Spice's virtual blocks are indeed based on preloaded parameterized subcircuit models. You can open the Netlist code of these subcircuits, copy or modify them and package them into your own new virtual blocks. You can even convert an entire circuit into a model complete with your own symbol. There are also a number of virtual blocks whose underpinning models have been hard-coded into RF.Spice's simulation engines and device manager. An important difference between black-box virtual blocks and user-defined devices or simulation models is that virtual blocks typically use idealized devices/models and a combination of linear and nonlinear sources to minimize circuit complexity regardless of the feasibility of their hardware realization. In other words, they are primarily intended to represent functional behaviors rather than practical circuits.

One of the great strengths of [[RFImage:Tutorial_icon.Spice A/Dpng|40px]] is the ease of creating new user-defined devices or models. Most of '''[[RF.Spice]]'s virtual blocks are indeed based on preloaded parameterized subcircuit models. You can open the Netlist code of these subcircuits, copy or modify them and package them into your own new virtual blocks. You can even convert an entire circuit into a model complete with your own symbol. There are also a number of virtual blocks whose underpinning models have been hardSpice_A/D#System-coded into [[Level_Tutorial_Lessons| RF.SpiceA/D System-Level Tutorial Lessons Gateway]]'s simulation engines and device manager. An important difference between black-box virtual blocks and user-defined devices or simulation models is that virtual blocks typically use idealized devices/models and a combination of linear and nonlinear sources to minimize circuit complexity regardless of the feasibility of their hardware realization. In other words, they are primarily intended to represent functional behaviors rather than practical circuits.''

A virtual block connects to the other parts of your circuit via its input and output pins. Most virtual blocks do not have a ground or reference pin. In that case, they are assumed to share the global ground. Almost all virtual blocks have input and output stages with either implicit or explicit input resistance and output resistance [[parameters]]. The default values of the input and output resistances are 10GΩ and 1μΩ, respectively. Obviously, these are unrealistic extreme values. The figure below shows the input and output stages of a typical virtual block. In cases where a virtual block does not provide explicit input and output resistance [[parameters]], you can add an external shunt resistor at the input and an external series resistor at the output. The large shunt resistor at the output is added to provide better stability for DC operating point analysis.

<td> [[Image:Diff0.png|thumb|left|640px|A generic macromodel with input and output stages.]] </td>

where v(t) and i(t) are the voltage and current of the capacitor, respectively, and C is it its capacitance. Similarly for an inductor, one can write:

<td> [[Image:Diff1.png|thumb|540pxleft|640px|An ideal differentiator using a capacitor.]] </td>

<td> [[Image:Diff2.png|thumb|540pxleft|640px|An ideal differentiator using an inductor.]] </td>

[[Image:Diff3.png|thumb|400px|A practical voltage differentiator circuit using an Op Amp.]] A more practical voltage differentiator circuit using an ideal operational amplifier (Op Amp) is shown in the opposite figurebelow. The voltage transfer function of this circuit is given by:

<table><tr><td> [[Image:Diff3.png|thumb|left|640px|A practical voltage differentiator circuit using an Op Amp.]] </td></tr></table> An equivalent macromodel of the above circuit is given in the following figure. This is [[RF.Spice]]'s "Analog Differentiator Block". In this model, the ideal Op Amp has been replaced with the linear controlled voltage source E2:

<td> [[Image:Diff4.png|thumb|700pxleft|720px|RF.Spice's "Analog Differentiator" block circuit.]] </td>

<table><tr><td> [[Image:Integ1.png|thumb|left|640px|A practical voltage integrator circuit using an Op Amp.]] </td></tr></table> An equivalent macromodel of the above circuit is given in the following figure, which represents [[RF.Spice]]'s "Analog Integrator Block". In this model, the ideal Op Amp has been replaced with the linear controlled voltage source E2:

<td> [[Image:Integ2.png|thumb|700pxleft|720px|RF.Spice's "Analog Integrator" block circuit.]] </td>

<td> [[Image:Integ3.png|thumb|700pxleft|720px|The block diagram of a generalized analog filter with a rational s-domain transfer function.]] </td>

[[RF.Spice]]'s "Generalized Analog Filter Block" does this realization automatically for any arbitrary filter order (or highest degree of the s-variable). You enter the denominator and numerator coefficients as arrays of real numbers. The figure below shows the property dialog of this black-box macromodel.

<td> [[Image:Integ4.png|thumb|left|560px|The property dialog of the generalized analog filter block.]] </td>

<td> [[Image:Integ5.png|thumb|700pxleft|720px|RF.Spice's "Digital Integrator" block circuit.]] </td>

<td> [[Image:Integ6.png|thumb|700pxleft|720px|The block diagram of a generalized IIR digital filter with a rational z-domain transfer function.]] </td>

[[RF.Spice]]'s "Generalized Digital Filter Block" does this realization automatically for any arbitrary filter order (or highest degree of the z-variable). Similar to the analog filter case, you enter the denominator and numerator coefficients as arrays of real numbers. But unlike the analog case, where the coefficients correspond to the powers of the s-variable, in the digital case the, you have to enter the coefficients for powers of (-z^1/2). In other words, if the orders of the numerator and denominator polynomials are M and N, respectively, then you need to define 2M+1 coefficients for the numerator and 2N+1 coefficients for the denominator. Obviously, the odd-indexed coefficients would be all zeros in a typical rational transfer function. But they don't have to be so. The figure below shows the property dialog of this black-box macromodel.

<td> [[Image:Integ7.png|thumb|left|560px|The property dialog of the generalized digital filter block.]] </td>

<td> [[Image:Integ8.png|thumb|700pxleft|720px|The block diagram of a generalized FIR digital filter.]] </td></tr></table> == Variety of Black-Box Virtual Blocks == [[RF.Spice A/D]] provides a large collection of black-box virtual blocks for different types of system applications. These have been loosely grouped into the following categories:  * '''Waveform Generation Blocks''': including sinusoidal, triangular and square wave chirp generators, random noise generator, random pulse generator, etc. * '''Analog Signal Processing Blocks''': including signal conditioning and transformation blocks, two-signal operations and signal feature detection blocks.* '''Digital Signal Processing Blocks''': including sampling blocks, discrete-time Fourier transform (DFT) and discrete convolution blocks * '''Spectral Processing Blocks''': including voltage controlled oscillators (VCO), frequency conversion blocks, generic filters, phase locked loop (PLL), etc. * '''Modulation Blocks''': including analog and digital modulations schemes (FM, QAM, FSK, DPSK, Delta-Sigma, etc.)  You can access all these blocks from the '''Parts Menu'''. Some of the waveform generator devices are categorized as "voltage source" devices in the Device Manager's point of view. A number of the virtual blocks are native XSPICE models. You can find their models as "process models" in the Device Manager. Many others are "subscircuit models". You can open up, view and even modify their Netlist codes. Some other blocks like the generalized analog and digital filters do not have editable Netlist codes.  == A Note on the SPICE Simulation of Virtual Blocks ==  Most of the virtual blocks can be used in both transient and AC analysis tests. Obviously, nonlinear operations must be performed in the time domain. For example, you can see the performance of voltage controlled oscillators (VCO) only in a transient test, and using them in conjunction with AC frequency sweep analysis is meaningless. The same is true for frequency conversion blocks such as frequency multipliers. In addition, certain blocks such frequency conversion blocks may require harmonic wave input signals and may not work properly with arbitrary waveforms.  When your circuit involves several interconnected virtual blocks, the SPICE simulation of your circuit is likely to encounter convergence problems. This is more frequent when you a transient analysis of such circuits. In those case, we recommend that you change the SPICE integration method. You can do this by opening the '''SPICE Simulation Options''' dialog from the Simulate Menu. There are two options available: trapezoidal or gear. The default option is "trap". Changing the integration method to "gear" can improve the convergence of the transient analysis.  <table><tr><td> [[Image:Integ9.png|thumb|left|640px|Setting the integration method in the SPICE Simulation Options dialog.]] </td>