You have certain level of control over the initial state of a digital circuit. The input pins of digital devices are always initialized to the Initial Unknown strength & level. You can set the initial state of the output pin of some digital devices such as latches and flip flops. This is done using the "IC" parameter of these devices, which usually has a default zero value.
<!--
==Power Dissipation==
In digital circuits, most of the power dissipated comes from the power source (VCC) through to ground. As a result, the current flowing into the VCC port of the device can be multiplied by the component's power level (5V) to give the component's typical power dissipation. In TTL (the standard and LS libraries in [[RF.Spice A/D]]), the power dissipation is fairly constant regardless of how often the circuit changes states. The power dissipated does depend to a certain extent on the state of the component (i.e., the voltage levels at the inputs and internal to the component), but [[RF.Spice A/D]] simply uses a constant to model power regardless of internal state. CMOS components dissipate power each time the state of a transistor changes. That is, the power dissipation of a CMOS component is closely related to the frequency at which the component's state changes. Be aware that the power dissipation for gates and flip flops are given on a per-gate basis. For example, if you have one 7400 in your circuit, the power dissipation will be 10 mW. However, if you were to build the circuit, you would need to use a full 7400 chip (4 gates), which would dissipate 40 mW.
For CMOS components, several approximations and assumptions have been made. Voltages at inputs of pins are assumed to be at CMOS voltage levels, i.e. within one volt of Vcc or ground. TTL high levels are more than 1 Volt from Vcc, which causes additional power consumption, but [[RF.Spice A/D]] ignores this. External capacitance is averaged over the output pins. As a result, if one pin has very high external capacitance, and it is changing frequently w/ respect to the other output pins, then the results will be too low.
The dynamic power dissipation factor is the component of total power dissipation that results from changes in the state of the component. In B2Logic , it is affected by the frequency of input changes, the power dissipation per gate (Cpd), the frequency of output changes, and the load capacitance. The formula used is:
total dynamic power = Vcc * (internal factor * input frequency + load factor * output frequency)
where:
internal factor = Vcc * Cpd.
load factor = Vcc * load capacitance.
load capacitance = average capacitance seen by an output pin of a device.
The output change count of a CMOS component is incremented by one each time an output pin changes its logic value (level or strength). The input change count is incremented by one each time one or more input pins change values. This is a rough approximation, since it doesn't take into account factors such as the voltage levels at the inputs, or the temperature, or the fact that for devices with multiple outputs, different pins have different loads, and these pins may change in concert, or one at a time.
-->
==Digital Clocks==
<p> </p>
[[Image:Back_icon.png|40px]] '''[[RF.Spice_A/D | Back to RF.Spice A/D Wiki Gateway]]'''
<!--
==Power Dissipation==
In digital circuits, most of the power dissipated comes from the power source (VCC) through to ground. As a result, the current flowing into the VCC port of the device can be multiplied by the component's power level (5V) to give the component's typical power dissipation. In TTL (the standard and LS libraries in [[RF.Spice A/D]]), the power dissipation is fairly constant regardless of how often the circuit changes states. The power dissipated does depend to a certain extent on the state of the component (i.e., the voltage levels at the inputs and internal to the component), but [[RF.Spice A/D]] simply uses a constant to model power regardless of internal state. CMOS components dissipate power each time the state of a transistor changes. That is, the power dissipation of a CMOS component is closely related to the frequency at which the component's state changes. Be aware that the power dissipation for gates and flip flops are given on a per-gate basis. For example, if you have one 7400 in your circuit, the power dissipation will be 10 mW. However, if you were to build the circuit, you would need to use a full 7400 chip (4 gates), which would dissipate 40 mW.
For CMOS components, several approximations and assumptions have been made. Voltages at inputs of pins are assumed to be at CMOS voltage levels, i.e. within one volt of Vcc or ground. TTL high levels are more than 1 Volt from Vcc, which causes additional power consumption, but [[RF.Spice A/D]] ignores this. External capacitance is averaged over the output pins. As a result, if one pin has very high external capacitance, and it is changing frequently w/ respect to the other output pins, then the results will be too low.
The dynamic power dissipation factor is the component of total power dissipation that results from changes in the state of the component. In B2Logic , it is affected by the frequency of input changes, the power dissipation per gate (Cpd), the frequency of output changes, and the load capacitance. The formula used is:
total dynamic power = Vcc * (internal factor * input frequency + load factor * output frequency)
where:
internal factor = Vcc * Cpd.
load factor = Vcc * load capacitance.
load capacitance = average capacitance seen by an output pin of a device.
The output change count of a CMOS component is incremented by one each time an output pin changes its logic value (level or strength). The input change count is incremented by one each time one or more input pins change values. This is a rough approximation, since it doesn't take into account factors such as the voltage levels at the inputs, or the temperature, or the fact that for devices with multiple outputs, different pins have different loads, and these pins may change in concert, or one at a time.
-->