Also note that "'''Step Size'''" is different from "'''Step Ceiling'''". Step size specifies how large each time step of the simulation is when using the "Simulation Stepping" feature. Step Size does not factor into the simulation when running the engine in "'''Walk'''" or "'''Run'''" modes, where the simulation engine itself decides how large a step to take. On the other hand, Step Ceiling is the maximum value that you specify for the automatically calculated time step when a simulation is "Walked" or "Run".
To set the step size, go to '''Simulate Menu''' and select the "'''Time Options...'''" to open the Simulation Time Options Dialog. Or click the button labeled {{key|...}} on the '''[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|Main Toolbar]]]]]]]]]]]]]]]]]]]]]]]]]]]]''' on the left of the Run button as shown in the figure below. You can also use the keyboard shortcut "Ctrl+I" to open this dialog, which is shown below:
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Start the [[Digital Simulation|digital simulation]] with all zero inputs and increment three time steps to 60ns. You will see that four timing diagrams appear at the bottom of the Workshop, one for each input and one for the output. In general every input and output port will have a timing diagram. Then, change the value of Input 1 to 1. Step again and you will see that the timing diagrams immediately get updated because the input states have now changed. Increment two more time steps to 120ns. Then, change the value of Input 2 to 1. Follow this recipe according to the above event table with 60ns intervals until all inputs are set to 0 again. The timing diagrams get updated after each change of state and the final diagrams are shown in the figure below. Note that your timing diagram may expand too long to fit into the bottom graph window. In that case, click on the title of the graph window tab to make it the active window. The toolbar changes accordingly. Then click the "'''Zoom Out Horizontal'''" [[File:b2ZoomOutHoriz_Tool.png]] button of the [[Graph toolbar|Graph Toolbar]] to shrink the diagram until it has the right size for viewing.
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{{Note|The timing diagram updates only when there is a change of states of the inputs.}}
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With a closer look at the output timing diagram, you will be able to see the propagation delay between the input and output ports. For example, at t = 180ns, when all three inputs are 1, you would expect to see the output to jump at 1. However, it takes about 20ns 19ns for this to happen (at t = 200ns199ns). To understand this, double-click on the NAND gate A2 and inverter gate A4 to open up its their property dialog dialogs as shown abovebelow. You will see that 74LS10D the generic NAND gate has a "'''Low-to-High Propagation Delay'''" of 9ns 11ns and a "'''High-to-Low Propagation Delay'''" of 10ns7ns. The 74LS04D Inverter has similar propagation delays. When Input 3 jumps to 1 at t = 180ns, it takes the NAND generic inverter gate has a propagation delay of 10ns "'''Low-to fall from its 1 state down to 0. Similarly, it takes the Inverter gate an additional propagation delay -High Propagation Delay'''" of 9ns to rise from its 0 state up to 1. This makes 12ns and a total delay "'''High-to-Low Propagation Delay'''" of 19ns as you can see from the graph. {{Note|The timing diagram updates only when there is a change of states of the inputs8ns.}}
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When Input 3 jumps to 1 at t = 180ns, it takes the NAND gate a propagation delay of 10ns to fall from its 1 state down to 0. Similarly, it takes the Inverter gate an additional propagation delay of 9ns to rise from its 0 state up to 1. This makes a total delay of 19ns as you can see from the graph.
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