Also note that "'''Step Size'''" is different from "'''Step Ceiling'''". Step size specifies how large each time step of the simulation is when using the "Simulation Stepping" feature. Step Size does not factor into the simulation when running the engine in "'''Walk'''" or "'''Run'''" modes, where the simulation engine itself decides how large a step to take. On the other hand, Step Ceiling is the maximum value that you specify for the automatically calculated time step when a simulation is "Walked" or "Run".
To set the step size, go to '''Simulate Menu''' and select the "'''Time Options...'''" to open the Simulation Time Options Dialog. Or click the button labeled {{key|...}} on the '''[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|Main Toolbar]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]''' on the left of the Run button as shown in the figure below. You can also use the keyboard shortcut "Ctrl+I" to open this dialog, which is shown below:
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== Analyzing the Propagation Delays ==
With a closer look at the output timing diagram, you will be able to see the propagation delay between the input and output ports. For example, at t = 180ns, when all three inputs are 1, you would expect to see the output to jump at 1. However, it takes about 19ns for this to happen (at t = 199ns). To understand this, double-click on the NAND gate A2 and inverter gate A4 to open up their property dialogs as shown below. You will see that the generic NAND gate has a "'''Low-to-High Propagation Delay'''" of 11ns and a "'''High-to-Low Propagation Delay'''" of 7ns. The generic inverter gate has a "'''Low-to-High Propagation Delay'''" of 12ns and a "'''High-to-Low Propagation Delay'''" of 8ns.