Also note that "'''Step Size'''" is different from "'''Step Ceiling'''". Step size specifies how large each time step of the simulation is when using the "Simulation Stepping" feature. Step Size does not factor into the simulation when running the engine in "'''Walk'''" or "'''Run'''" modes, where the simulation engine itself decides how large a step to take. On the other hand, Step Ceiling is the maximum value that you specify for the automatically calculated time step when a simulation is "Walked" or "Run".
To set the step size, go to '''Simulate Menu''' and select the "'''Time Options...'''" to open the Simulation Time Options Dialog. Or click the button labeled {{key|...}} on the '''[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|[[Main toolbar|Main Toolbar]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]''' on the left of the Run button as shown in the figure below. You can also use the keyboard shortcut "Ctrl+I" to open this dialog, which is shown below:
<table>
</table>
When Input 3 jumps to 1 at t = 180ns, it takes the NAND gate A2 a propagation delay of 10ns 7ns to fall from its 1 state down to 0. Similarly, it takes the Inverter gate A4 an additional propagation delay of 9ns 12ns to rise from its 0 state up to 1. This makes a total delay of 19ns as you can see from the graph. At t = 240ns, the reverse of these events happens and gate A2 and A4 undergo the opposite transition types. The total propagation delay is still 19ns, and therefore, the output drops from 1 to 0 at t = 259ns. These events are summarized in the table below.
{| class="wikitable"
! scope="col"| Total Delay
|-
| t = 180ns
| H -> L
| 7ns
| 19ns
|-
| t = 240ns
| L -> H
| 11ns