An example showing the delays for the 7404 inverter is shown in the figure on the right. In this case, TPLH = 8ns and TPHL = 12ns. You can see that as the input value changes from 0 to 1 at t = 20ns, the output value changes from 1 to 0 at t = 20 + TPLH = 28ns. subsequently, as the input value changes from 1 to 0 at t = 40ns, the output value changes from 0 to 1 at t = 40 + TPHL = 52ns.
[[RF.Spice A/D]] does not vary propagation delays depending on which input has changed value. For example, in an adder, when the carry-in input changes, the outputs respond more quickly than when other inputs change value. [[B2RF.Spice A/D]] cannot model this effect. Also, [[RF.Spice A/D]] cannot model delays when the output changes from indeterminate to low differently from changes from high to low. In the 74126 Bus Buffer with 3-State Outputs, for example, the time it takes for the output to change from its high impedance state to low (TPZL) is typically 15ns, while the time to change from high to low (TPHL) is typically 7ns. [[RF.Spice A/D]] does not allow specification of TPZL, so it uses TPHL in place of TPZL.
Many digital parts store their states regardless of what is happening at their inputs until a specific input changes value in a specific direction. The 7474 D flip flop is such a device. Its D input can change, but the output will not change until the clock pin rises from zero to one. We call the activating change in the clock pin a "Trigger". For the trigger to work, the circuit must be stable (i.e., inputs must not change) for a specific time period before the trigger occurs. This time is called the "Setup Time". After the trigger, the inputs must be stable for a time period so that the new state is not disturbed. This post-trigger time period is called the "Hold Time". If either the set up or hold time specifications are violated, the program notifies the user and sets the device's output to indeterminate.